In certain signal processing applications, such as an amplifier, a buffer circuit is required to reduce the output impedance of the amplifier to more closely match the input impedance of the device to which the amplifier is connected.
For example in a hearing aid, an amplifier is coupled between a microphone and a receiver. The microphone receives sound energy and converts the received sound energy to a corresponding electrical signal. The amplifier then amplifies the received electrical signal and the receiver converts the amplified electrical signal to amplified sound energy. In many such systems, the amplifier has a relatively high output impedance, and an output buffer is utilized to match the input impedance of the receiver. In fact, the closed loop gain of the amplifier is proportional to the output impedance of the amplifier. Thus the greater the closed loop gain of the amplifier, the greater the likely mismatch between the output impedance of the amplifier and the input impedance of the receiver.
In many circuits, conventional buffer circuits are satisfactory. However, many circuits operate at extremely low voltages. For example, circuits such as for hearings aids are designed for operation with a 1.1 volt battery. Thus V.sub.GS for the CMOS device in the buffer effectively limits the linear output range of the amplifier.
For CMOS devices, the surface potential in the channel can be modulated by either the gate or well potential. Normal operation usually biases the well (or bulk) at the same potential as the source (i.e., V.sub.SB =0), or the well to source junction is maintained in reverse bias. Maintaining zero or reverse bias from the source to well ensures that no carriers are injected laterally across the IC, which is a mechanism which leads to latch-up in CMOS circuits.
However, if the source to well (or bulk) potential, V.sub.SB, is forward biased and any laterally injected carriers are collected by heavily doped guard rings around the well, then latch-up is inhibited. This is especially true if the lateral current density is kept low, such as for small forward bias voltages for V.sub.SB (i.e., &lt;&lt;0.5 v). The well could then be used directly to modulate the surface potential in the channel region of an MOS device in a useful and enhanced manner.
When the well is tied directly to the gate and the MOS device is operated in weak inversion (sub-threshold), the ideality factor in the exponential I-V relation becomes nearly unity (as in the case of a bipolar transistor) since the surface potential becomes modulated directly by the gate to source voltage, instead of by an "effective" gate to source voltage formed by a capacitive divider between C.sub.ox and C.sub.depletion, wherein: EQU "effective"=V.sub.GS .times.C.sub.ox /(C.sub.ox +C.sub.depl).
This will result in improved g.sub.m for MOS devices operated in weak inversion.
Thus an effective, or dynamic, lowering of the threshold voltage, V.sub.T, for MOS transistors can be obtained in circuits by forward bias of the well to source junction. Enhanced transconductance equal to that of bipolar transistors can be expected if the well is tied to the gate and the MOS device is operated in weak inversion.
The present invention is provided to solve these and other problems.